1. Field of the Invention
This invention relates to buffer circuits employed in integrated circuits and, more particularly, to the automatic control of the drive strength of buffer circuits. The invention also relates to methods for controlling the drive strength of a buffer circuit.
2. Description of the Related Art
A digital circuit is fast or slow relative to the time allotted by the overall system requirements. In microprocessors, the time allotted to logic is usually measured in periods or fractions of a period. If a circuit is just fast enough to operate at 5 MHz, for example, then it is a "fast" circuit if used at an operating frequency of 1 MHz and a "slow" circuit if used at an operating frequency above 5 MHz.
For a given operating frequency, a circuit is fast or slow due to several factors. First, semiconductor processing variations give rise to variations in the speed of circuits. This, of course, is fixed for a given device, but the speed of a randomly selected device is not entirely predictable due to these manufacturing variations. Second, the operating temperature of a device affects its speed. This is a parameter that varies from application to application and also within a given application over time. The operating voltage of a device also affects its speed. This parameter also varies from application to application and over time within a given application.
Buffer circuits are logic gates in integrated circuits that have the primary function of driving signals. Two important examples of buffer circuits are circuits that drive clocks and circuits that drive semiconductor device outputs. In both of these instances, the buffer circuit provides the large drive currents necessary to quickly drive signals with relatively large loads.
In practice, such buffer circuits must be designed to drive the maximum expected load in the minimum expected time such that the semiconductor device can meet its specification under worst-case conditions and over the expected range of variation in relevant manufacturing parameters. However, during actual operation, the manufacturing parameters, operating conditions, operating frequencies and loads on these signals are often not worst-case. In such cases, the designed buffer drive strength is excessive. Excessive drive strength can be problematic in several ways.
Excessive drive strength on signals that carry periodic waveforms results in excessive electromagnetic interference (EMI). This in turn complicates the design of systems by requiring the addition of shielding or by requiring further optimizations to the design and layout of circuits in the system.
Excessive drive strength on signals also increases the amount of power supply noise present on the chip and in the system. This reduces noise margins in the system.
Lastly, excessive drive strength causes signals to have faster edge rates and more ringing. These characteristics create transmission line problems in the system which must be addressed by the system hardware designers.